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Advanced SoC/IP Design and System Integration
Given the development of process technology in IC fabrication and strong demand for SoC design services, EDA vendors continue upgrading the corresponding EDA tools and design technology. CIC has long worked with major global EDA vendors and integrated their EDA design tools into different IC/System design flows. Consequently, designers can easily sketch their design concepts, use EDA tools and design flows, and tape out chips to realize their IC/System designs. To save time during the design process, CIC actively integrates and remodels design flows for academic use. The purpose is to provide enhanced IC design solutions.
In order to reinforce and update the design environment, 10 new EDA software (as Table 7) had been introduced in 2007 and one EDA software has been weeded out (That is, VN software of TransEDA is replaced by Assertion ABV of TransEDA).
The following Electronic Design Automation (EDA) tools were introduced in 2007: (1) Cadence SiP Digital Architect, SiP Digital Layout, SiP Digital SI, SiP RF Architect, SiP RF Layout, Virtuoso Analog HSpice Interface Feature,DIVA, and Conformal GXL. (2) CoWare Platform Architect Run-Time Feature. (3) TransEDA Assertion ABV. Additionally, the CIC is also working to upgrade design flows of the Cell-Based IC, Platform-Based SoC, System-Level, Full-Custom IC, Field-Programmable Gate Array (FPGA), Mixed-Signal IC, Radio Frequency/ Monolithic Microwave Integrated Circuit (RF/MMIC), and MEMS.
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