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CIS Design

  Compared with Charge Coupled Device (CCD), the CMOS image sensor has many advantages such as low power, low cost, and high integration capacity. Although CCD provides relatively higher resolution, the advantages of the CMOS process have narrowed the gap between CCD and CMOS. Previously, CMOS image sensors have had important roles in numerous applications. Due to the significant progress in CMOS image sensors process, CMOS image sensors have replaced CCD image sensors in numerous applications.

  The CCD image sensor modules were mostly used as components on artificial satellites for remote sensing, whereas some satellites have adopted COMS images sensors in recent years. A remote sensing system transforms remote sensing images to a local display via many complex procedures in signals processing. Figure 37 shows the signal processing flow in a remote sensing system. First, the scene is detected by a sensing array; the sensing array then transforms information from light into a charge, and the number of charges corresponds to light strength. After amplifying the sensed signal via analog processing, a consequent Analog-to-Digital Converter (ADC) circuit converts the signal from analog to digital. Last, digital signal processors and computing systems transform the electrical signals to visual frames. Adopting the CMOS process can effectively reduce the complexity due to the integration capacity of the CMOS image sensor process.


  In 2006, CIC developed a remote satellite sensing module that was realized in the 0.18µm CMOS image sensor process. First, an ADC was taped-out to confirm the integration capacity of the CMOS image sensor process. Based on measurement results, the circuits were integrated into a CMOS image sensor process. This study also performed the second version of this remote sensing subsequently. In this version, the active pixel array is realized by using a Four Transistor (4T) structure. The pixel and analog circuits are integrated in this version to achieve remote sensing functionality. This design has been taped-out and its performance will be measured following chip fabrication.