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CMOS MEMS Design
The CIC CMOS MEMS process comprises a standard CMOS process and a micromachining post-process. The primary materials for metallic and dielectric layers in the CMOS process are aluminum and silicon oxide, respectively. The post-micromachining process consists of anisotropic oxide etching and isotropic silicon etching. Figure 31, an example, lists the cross-sectional view of the 0.18µm CMOS MEMS process flow. In the CIC CMOS MEMS process, an additional photoresist layer is spun and lithographed, and this photoresist layer is utilized to design rules, lateral-to-vertical etching behavior, process definition of the simulation tool (by CoventorWare), and process design guidelines are currently available to designers. In the 0.18µm CMOS MEMS process, 12 CMOS MEMS inductors based on foundry device libraries have been verified and integrated into the design kits. In 2006, CIC started extracting material parameters such as Young’s modulus and equivalent residual stress of the compound layers in CMOS. Extraction results will be updated in the design kits for the CIC CMOS MEMS process in 2007. The process should assist designers when modifying simulation errors and be closed to real conditions. Figure 32 shows some SEM photos of devices based on the CIC CMOS MEMS process. In RF circuit design, CIC has also confirmed that the CMOS MEMS inductor improves RF circuit performance. Figure 33 is the quality factor for standard CMOS and CMOS MEMS inductors. The 5.8GHz VCO with the CMOS MEMS inductors makes a 5dB improvement in phase noise compared with that of standard CMOS VCO circuits.
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