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Electronic System Level (ESL) Design
The "Electronic System Level" (ESL) design extensively means the system modeling and hardware/ software co-design above the Register Transfer Level (RTL) implementation. With high abstraction level hardware description languages (such as SystemC or LISA) and plentiful IP libraries, the ESL methodology provides a rapid prototyping environment for exploring the most efficient architectures in the early stage of the design flow, even when the real hardware is not ready yet. After the system architecture is decided, hardware developers further implement individual IPs, while the software developers develop the applications with a software-based rapid simulator (i.e. virtual platform) built by the ESL tools. Thus, the development cycle is shortened and the failure risk of project is reduced.
The ESL tool usually provides two simulation models; both are based on the Transaction Level Modeling (TLM) technique. The Cycle-Accurate (CA) model insures the timing accuracy of the simulation to the cyclecount level. This kind of model is usually used for the performance analysis and TLM/HDL co-simulation, where simulation time should be fast, but the behavior of each IP modules in the virtual platform must be identical to its respective hardware specification. For software developers, the execution of operating system and applications leads to the need of a much faster simulation speed, but the timing behavior of hardware signals are not concerned. The Instruction-Accurate (IA) model provides a pure-software simulation environment which performs even faster than the FPGA-based prototyping tools.
In 2007, we introduce the virtual prototyping stage in the MP-SoC-II design flow. Several ESL functionalities such as architecture exploration and IP implementation in Transaction Level Modeling (TLM) are omitted due to following facts:
1. The architecture of the MP-SoC platform is pre-defined.
2. All project IPs are already implemented in Verilog.
The first objective of the virtual prototyping stage is to verify the logic-level correctness of project IPs with the ESL simulation tools. All Verilog-based IP modules are packed with TLM interfaces and connected to SystemC-based platform in the simulation environment as demonstrated in Figure 23. Each project IP is verified by a pattern generating software. The SystemC/Verilog co-simulations are much faster than pure Verilog simulations, which provide more opportunities for IP designers to refine their works.
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