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IP Center
For SoC/IP research, the center has actively established an IP Center (IPC) on the web site (http://ipc. cic.org.tw:2647). The early stages of IPC were established, including five reference Silicon IPs (SIPs) created by the center, and ARM922T imported from ARM. The five reference IPs include ADC, DAC, MPEG4 shape encoder, audio codec, and MPEG4 codec. Additionally, the 32-bit RISC ARM7TDMI and ARM926EJ CPU from ARM were introduced for academic use in 2006. Accordingly, users can design their own soft/hard IPs using those reference SIPs. Moreover, IP Integrators can also develop the specific SoC design with ARM7TDMI, ARM926EJ or S+Core5U.
To date, CIC has closely collaborated with various academic research groups to develop various key SIPs. These SIPs include a wavelet-based adaptive visible watermarking processor, a high-performance variable-length cached-FFT processor, a reconfigurable IP core for MPEG-4/AVC H.264 transform coding, a Reed-Solomon codec, an All-Digital Phase-Locked Loop (ADPLL), a Reed-Solomon Codec, a flexible Single-Instruction Multiple- Data (SIMD) functional unit, a Synchronous Dynamic Random Access Memory (SDRAM) controller and a pseudo random pattern generator with a PLL clock. These SIPs are introduced into the CIC IP Center and then reused in academic research. This year CIC has also cooperated with several universities to design various SIPs including an embedded memory Built-In Self-Repair, a Fast Fourier Transform (FFT), a low-cost H.264 video decoding system, an area efficient AMBA bus tracer, and a low-cost and low-power 32-bit RISC. Additionally, to ensure the quality and completeness of the SIP design, CIC edited a Cell-Based SIP checklist, which shows the details for IP implementation, hardware integration, software integration, and rapid prototyping deliverables. Thus each team can follow this checklist to complete a deliverable SIP design.
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