Regarding the research and development of SoC/SIP, CIC aims to establish a design and verification environment for Multi-Project SoC (MP-SoC) for resource sharing and cost reduction. MP-SoC integrates heterogeneous SoC projects onto a single chip with shared CPU, DSP Core, Memory, On-Chip Bus, DMA, and so on. The designs, successfully achieve their goals of verification and measurement, for different projects are re-delivered into soft or hard IPs.

        To realize this MP-SoC design concept and methodology, four universities in Taiwan (the NationalTaiwanUniversity, NationalChungHsingUniversity, NationalChengKungUniversity, and NationalSunYat-SenUniversity) took part in this MP-SoC project. In total, eight IPs (i.e., eight SoC projects) from the four universities were selected to share the common SoC platform, which includes a Advanced Encryption Standard (AES) engine for communication systems, a Discrete Wavelet Transform (DWT) engine for image compression, a Reduced Instruction Set Computer (RISC) processor (A7 RISC) for system control, a Scaled Discrete Cosine Transform type IV (SDCTIV) and a Inverse Modified Discrete Cosine Transform (IMDCT) engine for MP3 application, two Advanced Test Platforms (ATP) for SoC testing, and a Motion Estimation (ME) engine for video compression. This MP-SoC-I platform is capable of handling various applications, such as communications, image and video/audio processing, and SoC testing. Figure 17 shows the MP-SoC-I block diagram.

Figure 17 - MP-Soc-I Block Diagram

Figure 18 - MP-SoC-I Chip Photo

        The MP-SoC-I chip was fabricated using the TSMC 0.13μm 1P8M logic process. Chip core size is roughly 3700×37003 μm2 and overall chip size, including the I/O pads, is 4950×49384 μm2. The total number of I/O pads is 256, comprising 104 power pads and 152 signal pads.

        Figure 18 shows the microphotograph of the MP-SoC-I chip. This MP-SoC-I chip was tested in two environments - one was via Agilent 93000 ATE equipment, and the other was using a customized development board. Figures 19 and 20 show the load board of the Agilent 93000 and the customized system development board, respectively. When the chip was measured on the ATE, the input patterns were the same as those captured in advance during the Verilog simulation. Chip output results captured by the ATE were then compared with expected patterns obtained from the Verilog simulation. The other method of measuring the MP-SoC-I chip was using the system development board. At test start, .ash memories were initialized with the application software. The host PC then performed the source-level debugging of the MP-SoC chip via the multi-ICE connector. The logic analyzer and pattern generator were utilized to assist the measurement job.

        Measurement results indicate that the chip successfully operates at 10ns clock cycle time (i.e., 100 MHz clock rate). The ARM922T CPU (the CPU of the common platform) occupies a large fraction of total chip area (Fig. 18). Approximately 82.91% of the silicon area is saved when adopting the MP-SoC concept compared with the case in which multiple SoC projects are fabricated individually. To share this successful MP-SoC result, an MP-SoC workshop was held in March, 2006 and attending professors were invited to share their experiences. Figure 21 shows the MP-SoC workshop. Currently, the CIC is collaborating with seven academic research groups (11 SoC projects) to design the second-generation MP-SoC chip (MP-SoC-II).

Figure 19 - Agilent 93000 Load Board with the MP-SoC-I Chip

Figure 20 - MP-SoC-I System Development Board

Figure 21 - SoC Workshop