Regarding the research and development of SoC/SIP, CIC aims to establish a design and verification environment for Multi-Project SoC (MP-SoC) for resource sharing and cost reduction. MP-SoC integrates heterogeneous SoC projects onto a single chip with shared CPU, DSP Core, Memory, On-Chip Bus, DMA, and so on. The designs, successfully achieve their goals of verification and measurement, for different projects are redelivered into soft or hard IPs.

　　To realize this MP-SoC design concept and methodology, four universities in Taiwan took part in the first MP-SoC (MP-SoC I) project in 2006. In total, eight IPs (i.e., eight SoC projects) from the four universities were selected to share the common SoC platform. Experimental results reveal that our MP-SoC-I test chip can save a lot of commonly used silicon area and hence can greatly increase the cost-efficiency of the SoC. Besides, this MP-SoC design concept is very helpful for the SoC design teams in academia since it greatly enhances the silicon prototyping opportunity for the SoC design projects.

　　In 2007, to further demonstrate the efficiency of our MP-SoC design concept, we collaborate with more academic research groups (eleven academic research groups, i.e. 11 SoC projects) to design the second MP-SoC (MP-SoC II) chip. The IPs from these universities include an H.264 decoder (H264) for video coding, an on chip switch (SWITCH) for network on chip, a shape adaptive zero tree coding engine (BUZTC) for image processing, a common filterbank IP (CCFP) for Multi-Audio Standards, a context adaptive binary arithmetic coding engine (CABAC) for video compression, a fast Fourier transform (FFT) for communication system, a RISC processor (RISC32) for system control, an advanced test platforms (ATP) for SoC testing, a memory built in self repair for memory testing, an transport stream processor (VIDEO) for digital TV application, and a 6-b 250-M sample/s analog-to-digital converter (ADC) for data conversion. Figure 19 illustrates the MP-SoC II block diagram. Note that the solid blocks present the shared system blocks, while the dashed blocks are reserved for individual IPs from the universities.