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Processes for Prototyping IC Fabrication
In 2007, including five Silicon CMOS, one SiGe BiCMOS, two CMOS MEMS, and one GaAs processes, were provided by CIC for prototyping IC manufactures with the aim of continuously enhancing the IC design ability of academic institutions in Taiwan. The process features are as follows:
(1) TSMC 0.13µm Mixed-Signal/RF Process
To date, this advanced CMOS process is provided only for users with project relationships with CIC. This process employs one poly layer and eight Metal layers. TSMC 0.13µm Mixed-Signal/RF Process uses core supply voltage 1.2V, and I/O of 2.5V. To reduce RC delay and thus improve performance, TSMC offers low-k inter-metal dielectrics and all copper interconnect for 0.13µm technology. The thick top metal is provided optionally for RF applications. Although the process is suitable for Mixed-Signal and RF applications, the TSMC 0.13µm Mixed- Signal/RF Process is fully compatible with the standard 0.13µm logic process, owing to the provision of multiple Vt devices, MiM capacitors, poly resistors with high resistance, thick metal inductors.micro;
(2) TSMC 0.13µm Mixed-Signal/Logic Process
To date, this advanced CMOS process is provided only for users with project relationships with the CIC. This process employs one poly layer and eight metal layers. The TSMC 0.13µm Mixed-Signal/Logic Process utilizes a core supply voltage of 1.2V, and I/O of 3.3V. To reduce RC delay and thereby improve performance, TSMC offers a low-k inter-metal dielectrics and all-copper interconnects for the 0.13µm technology. The process is suitable for Mixed-Signal and logic applications, owing to the provision of multiple Vt devices, MiM capacitors, and poly resistors with high resistance.
(3) TSMC 0.18µm Mixed-Signal/RF Process
Provided in the form of TSMC MPW shuttles, this advanced CMOS process has been officially released for the applications of academic and industrial users. In 2004, CIC provided two runs of full-mask prototyping for high research requirement. This process employs single poly layer and six metal layers with low-k inter-metal dielectric. Deep N-well, MiM capacitors, poly resistors with high resistance, multi-Vt devices and thick top metal layers are available for 1.8V/3.3V applications. The process is also fully compatible with the 0.18m standard logic process, and is suitable for logic, Mixed-Signal, and RF designs.
(4) UMC 0.18µm Mixed-Signal/RF Process
This CMOS process is only available to academic users since it is fabricated through UMC provided shuttle. This process possesses one poly layer and six metal layers with low-k inter-metal dielectric. This process features deep N-well, multi-Vt devices, MiM capacitors and thick top metal (20KA) inductors are available for 1.8V/3.3V applications. The proposed process is suitable for logic, Mixed-Signal, and RF designs.
(5) TSMC 0.35µm Mixed-Signal Polycide Process
This CMOS technology is suitable for manufacturing two poly layers and four metal layers. Additional poly layers are employed to realize PiP capacitors. The proposed process is suitable for both logic and Mixed-Signal designs in 3.3V/5V.
(6) TSMC 0.35µm SiGe BiCMOS Process
This SiGe BiCMOS Process involves the manufacture of three poly layers and three metal layers, and is fully compatible with the 0.35µm CMOS logic process. The process involves three NPN bipolar devices with a unit gain frequency (FT) of 62/40/25GHz (HS/ST/HV) and a unit power gain frequency (Fmax) of 70/60/40GHz at different breakdown BVCEO voltages (> 2/3/5V). Two poly resistors (Hi/Lo) and Metal-Insulator-Metal capacitors are supported. Notably, deep trench isolation provides superior noise immunity in bipolar devices, and is a key consideration in RF designs.
(7) 0.18µm CMOS MEMS Process
The CIC CMOS MEMS process is fabricated by TSMC 0.18µm 1-poly 6-metal CMOS process and CIC post micromachining process. The mechanical microstructures are made of the metallization and dielectric layers of CMOS. To avoid the stiction in wet etching process, the anisotropic and isotropic dry etching are both employed to release the mechanical microstructures after CMOS process.
(8) 0.35µm CMOS MEMS Process
The CIC CMOS MEMS process is fabricated by TSMC 0.35?m 2-poly 4-metal CMOS process and CIC
post micromachining process. The mechanical microstructures are made of the metallization and dielectric layers
of CMOS. To avoid the stiction in wet etching process, the anisotropic and isotropic dry etching are both employed
to release the mechanical microstructures after CMOS process.
(9) WIN 0.15µm pHEMT Process
WIN is a world leader in GaAs using advanced 6-inch low-noise and power pHEMT technology for high speed and high performance MMIC and RF ICs. The 0.15µm low-noise pHEMTs are suitable for broadband communications and can implement very low noise and high gain LNAs with operating frequencies ranging up to 100GHz. Moreover, the 0.15µm power pHEMTs, which are well suited for applications in Local Multipoint Distribution System (LMDS), Multipoint Video Distribution System (MVDS) and automotive radar, can achieve high-power performance of up to 100GHz.
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