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RF Front-End IC Design
In 2006, CIC developed a complete system-integrated design and verification environment for RF SoC/SiP. During the circuit design phase, post-layout simulation flows with parasitic extraction for RF circuits was developed and verified using several common circuits, Low Noise Amplifier (LNA), mixer, polyphase filter, and VCO. As the target of uni-platform design environment, this post-layout simulation flow was developed based on the Calibre/Composer platform with the capability of supporting three simulators - ADS/RFDE, Spectre/SpectreRF and HSPICE/HSPICERF (Fig. 27). This post-layout simulation flow provides RF circuit designers with a simple and reliable solution for estimating the effects of low GHz parasitic resistance and parasitic capacitance in designed circuits. During the system design phase, the focus was on developing a design and verification environment for a wireless RF/analog front-end system. Direct conversion topology of the wireless RF/analog front-end system conforms to IEEE 802.11a, which was utilized as a design example for verification. Based on the IEEE 802.11a standard, the system front end must meet the sensitivity requirement and test results for Adjacent Channel Interference (ACI), Alternate Adjacent Channel Interference (AACI), and blocking. In addition to the fundamental tests for the receiver front end, designers can modify the other system parts, including digital or other RF/analog parts, for detail analyses.
For the RF front-end design, CIC is continuously generating complete and reliable hardware and software infrastructures for a fully-integrated and fast design environment spanning top-level system design to bottom-level circuit design for the academia.
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