SIP Design
In collaboration with the National SoC Program, CIC collaborates with various academic research groups to create reference SIPs. Professors and students thus can easily integrate reference SIPs to produce their SoC designs. Finally, these SoC designs can be realized through the Multi-Project SoC (MP-SoC) projects of CIC. In 2007, six SIPs were available on the CIC IP Center for reference. These structural insulated panels (SIPs) include a Memory Built-In Self Repair (MBISR), a RISC32 CPU, a MMTC1 FFT, a MMTC2 CABAC, an AMBA on-chip signal/event tracer (BUS Tracer), and a H.264 decoder interpolator for embedded system.
(1) Memory Built-In Self Repair (National Tsing Hua University)
After Reset, the MBIST (Memory Built-In Self-Tester) will start to test the back-up memory, and subsequently the main memory. MBISR retrieves the damaged sectors as detected by MBIST and calculate the corresponding relationship between the damaged sector and back-up according to the back-up configuration algorithm without delaying testing time.
After testing finished, the external can access immediately the memory to be tested normally. When accessing to the damaged sectors, the MBISR will switch to the back-up memory in alternate for recovery in time.
The IP consists of 6 features:
(a)Fast in time analysis without taking testing time, which is unlike common repairing circuit needs to hold for
testing. Completely without extra time span for analysis (Synthesis: .13,500 MHz)。
(b)Extremely less amount of optional logic area. For a memory of 16 KWORDS to be test at back-up
memory of 4 Elements (applicable to two directions in row and column), the optional logic area is only
0.36%. Besides, after At-speed & Programmable BIST, the area will be less than 1/3 of the ITRS strict STD
(35/3 Kgates/ MbitsMemory).
(c)Efficient configuration algorithm. 2-dimension back-up configuration in two directions of row and column is
the main stream as accredited in future. However, due to the uncertain distribution of the damaged
memory, searching the optimal configuration has been certified to be the issue of NP-Complete. Particularly
under the premise of build-in automatic execution, chip area and analyzing time is limited, it is required to
adopt a simple but efficient method to attain high recovery rate.
(d)The revolvable 2-dimension back-up structure which can recover the damaged row or column and meet the
mechanism requirement until 2011 as predicted by ITRS with using logic correspondence to fix the damages
in row or column two directions by a corresponded back-up core.
(e)Support ARM AMBA 2.0. After reset the automatic test mechanism of soft-repair may save the cost of
nonvolatile memory. Therefore, in order to avoid the memory in access testing with errors, collocates a
special memory controller. Also with Interrupt mechanism which enables ARM without waiting for the testing
time as well as polling result during the testing period but getting the result after testing completed which
to improve the ARM performance efficiency.
(f)Circuit generator. Collocate the auto RTL circuit generating program and adjust spec. according to the
input.
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