SiP Design

　　In terms of chip and package assembly, CIC utilizes flip-chip technology (Figure 34) to ensure that chips adhere to the packaging substrate. Currently, TSMC provides CIC with flip-chip bumpers on cyber shuttles for 0.18µm CMOS technology.

　　Conventionally, the design of multi-layer packaging is completely isolated from the IC design environment. A SiP approach is typically implemented in two separate domains, one for IC design and one for packaging design. This separation results in most bugs related to interface between chips and packaging are detected only when designers begin assembling the chips and packaging. One frequently occurring example is that the locations of chip pads differ from those on packaging. When chips and packaging are designed in two different domains, such problems are very difficult to detect during the early design stages

　　The following are actions that have been undertaken regarding the embedded passives in Low Temperature Co-fired Ceramic (LTCC) substrates (Figure 35).

　　First, the layers for LTCC design are integrated with chip design layers released by foundries into a single tech. le. This new techfile was created by including all required drawing layers for LTCC technology. The layouts of the embedded passives were then be generated using PCells encoded in the Cadence dfll environment. The types of embedded passives include spiral inductors, helical inductors, circular inductors, half-turn inductors, Metal-Insulator-Metal (MiM) capacitors, vertical-inter-digital capacitors, and coplanar waveguides (Figure 36). This study also developed a user-friendly flow for importing 3D structures into EM simulators from the Cadence environment. Since the layouts of embedded passives have been parameterized, the layouts needed quickly could be generated systematically in the design environment. A close link is maintained between EM simulators and the Cadence dfll database. Both the 3D EM simulators and the Cadence dfll environment have the same features, as the 3D structure of passives are converted directly from the GDS-II format layout generated by the dfll environment. Finally, the first version of the DRC deck was generated for LTCC layout verification.