There are four Silicon CMOS, one SiGe BiCMOS , and three GaAs processes offered by CIC for prototyping IC manufactures in 2002. The selected processes are well developed and applicable for VLSI circuit development. Their features are introduced as follows:

(1) TSMC 0.18um Mixed Signal/RF Process:

  This CMOS process provides academic users only as it is fabricated through TSMC provided shuttle. It possesses 1 poly layer and 6 metal layers with low k inter-metal dielectric. Deep N-well, MiM capacitor, high poly resistor, multi-Vt device and thick top metal are available for 1.8V/3.3V applications. It is suitable for logic, mixed signal, and RF designs.

(2) TSMC 0.25um Mixed Signal/RF Process:

  This CMOS process provides academic users only as it is fabricated through TSMC provided shuttle. It supports 1 poly layer and 5 metal layers and provides designers with excellent performance and lower cost than expensive BiCMOS and GaAs processes. Deep N-well, MiM capacitor, high poly resistor, multi-Vt device and thick top metal are available for 2.5V/3.3V applications. It is suitable for logic, mixed signal, and RF designs.

(3) TSMC 0.35um Logic Silicide Process:

  1 poly layer and 4 metal layers are supported in this technology. The features of silicided source-drain is profitable for 3.3V logic designs. The silicided difussion is blockable by the definition of additional mask.

(4) UMC 0.5um Mixed Signal Process:

  This CMOS technology provides the manufacture of 2 poly layers and 2 metal layers.
  Additional poly layer is used to realize PiP capacitor. This process is suitable for both logic and mixed signal designs in 5V systems.

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